The present invention relates in general to digital communication systems, and is particularly directed to a new and improved multiplexerxe2x80x94demultiplexer (mux/demux) protocol and mux/demux communication arrangement therefor for enabling a pair of high bit rate digital subscriber line (HDSL)-formatted data channels and an associated embedded operations channel (EOC) to be transported over a serialized communication link, such as one associated with wireless (e.g., radio, fiber optic) communication equipment.
FIG. 1 diagrammatically illustrates a conventional HDSL network architecture for conducting (duplex) communications between a xe2x80x98controlxe2x80x99 or head end site 10 and a remote site 20. At the head end site 10, a control terminal or HTU-C 11 is coupled to a first location (e.g., a relatively xe2x80x98westxe2x80x99 end, as viewed in FIG. 1) of a pair of HDSL wireline pairs 33 and 34; similarly, at the remote site 20, a remote terminal or HTU-R 21 is coupled to a relatively xe2x80x98eastxe2x80x99 end of the HDSL wireline pairs 33 and 34. The two HDSL wireline pairs carry time synchronized 784 kbps HDSL channels, each of which consists of a 772 kbps data channel and a 12 kbps overhead (embedded operations) channel used for auxiliary communications, such as status monitoring and provisioning. Where the two sites are spaced apart by a relatively large distance, one or more repeater or HRE equipments sites, two of which are shown at 40 and 50, may be installed in each of the wireline pairs.
Because of a number of limitations in using wireline links (including link availability, confined bandwidth, and the need for repeaters for extended distance communications), digital communication service providers have been turning to wireless transmission architectures, such as radio wave and fiber optic links. Unfortunately, the channelized data structures and protocols employed by some digital communication formats, such as HDSL, do not readily lend themselves to schemes which are designed to accept and transmit asynchronous, serialized data signals. As a result, the two wireline links 31 and 32 of the network architecture of FIG. 1 cannot simply be severed in the vicinity of the two sites, as shown by broken lines 35 and 36, and then connected to wireless (e.g., radio) equipments 12 and 22 that are designed to transmit and receive (modulated) serialized and asynchronous digital data.
In accordance with the present invention, this problem is effectively solved by processing the two HDSL channels in accordance with a prescribed serialized multiplexerxe2x80x94demultiplexer protocol, that enables both HDSL channels to be successfully transmitted over an asynchronous, serialized communication link. The serialization protocol employed by the present invention includes an additional service channel to convey control information used by a far end device to properly extract and reassemble each HDSL channel from the serialized bit stream.
The HDSL-serialized multiplexer portion of the HDSL mux/demux arrangement of the present invention includes a data channel interface circuit, which is operative to interleave a pair of 772 kbps data channel segments of two 784 kbps HDSL channels into a standard 1.544 Mbps T1 serial data stream. This T1 data stream is buffered through a first-in, first-out register or FIFO for application to an output multiplexer. The FIFO provides for clock rate adaptation of the regular T1 data stream with irregular T1 payload possibilities in the protocol. The data channel interface circuit also contains an internal register bank which stores embedded operations channel (EOC) information extracted from the two HDSL channels.
Auxiliary HDSL signaling information stored in the register bank of the data channel interface circuit is controllably accessed by a communications control processor for application to the output multiplexer. HDSL EOC information and service channel information are coupled through associated universal asynchronous receiver/ transmitters or UARTs for application to the output multiplexer. In addition, a processor-controlled framer unit supervises the operation of output multiplexer controllably and injects auxiliary (framing and time alignment) service channel signals to the output multiplexer.
The framing structure of the serialized HDSL protocol of the present invention provides a contiguous sequence of bits, and includes framing bits, HDSL asynchronous channel bits, bit-stuffing majority bits, a stuffing bit, a signaling bit, and 1.544 Mbps T1 payload bits. In order to accommodate the additional signaling bits of the serialized HDSL protocol framing structure of the invention, the multiplexer employs an increased bit rate (on the order of 1.710 Mbps). The framing bits are employed for frame alignment, while the HDSL asynchronous channel bits provide an asynchronous channel for transporting the HDSL EOC bits. The signaling bit provides an auxiliary, independent signaling channel. The bit-stuffing majority bits and the stuffing bit bits supplied by the framer provide bit justification of the T1 data stream. The increased bit rate serial data stream produced by the output multiplexer is coupled to downstream serial communication equipment, such as a fiber optic transmitter or a digital data radio.
At the receive end of the serial link a demultiplexer is coupled to receive the increased bit rate (e.g., 1.710 Mbps) serialized HDSL data stream supplied from upstream serial communication equipment, such as an associated fiber optic transmitter or digital data radio. The demultiplexer is controlled by a frame sync detector and a frame generator. The frame generator uses its knowledge of the protocol framing structure to steer the respective bits of the incoming serialized data stream to a set of output ports. To ensure proper sequencing among the respective output channels, the frame generator defaults the demultiplexer path to the frame sync detector.
Using the bit-stuffing majority bits and stuffing bits for timing alignment, the frame sync detector compares the supposed positions of the framing bits with a prescribed framing pattern, and xe2x80x98pausesxe2x80x99 the operation of the frame generator, until the supposed framing bits match the framing pattern for a predetermined number of consecutive frames. Once the framing pattern has been located, the frame generator is allowed to controllably steer the contents of the incoming serialized data stream to its output ports. One output port is coupled to an associated UART which supplies independent signaling channel bit.
Another output port is coupled to a UART, which supplies HDSL asynchronous channel bits that carry the HDSL EOC information to a microcontroller for storage in associated registers of a T1 demultiplexing ASIC. A further demultiplexer output port supplies the T1 data stream through a FIFO to the T1 demultiplexing interface ASIC. The demultiplexing interface ASIC demultiplexes the two interleaved (784 kbps) HDSL channels and their associated EOC information to individual HDSL channels at a pair of output ports for application to a downstream HTU.